Keithley 2474 EOT WP free download

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WHITE PA P E R Integrating high frequency capacitance measurement for monitoring process variation of equivalent oxide thickness of ultra-thin gate dielectrics Yuegang Zhao Keithley Instruments, Inc. Introduction As CMOS transistors have gotten smaller and smaller, so has the thickness of their gate dielectrics. This presents a great challenge to traditional capacitance measurement used to monitor dielectric thickness for process variation. First, the relationship between the capacitance value in the inversion or accumulation region of the capacitance-voltage (C-V) curve to the gate oxide thickness is no longer simple. It's necessary to apply new models, including quantum mechanics and polysilicon depletion effects, to determine oxide thickness accurately from the C-V curve [1, 2]. Second, gate leakage increases exponentially as thickness decreases due to tunneling of carriers through the ultra-thin gate [3]. The gate capacitor becomes very lossy due to high leakage, and the gate capacitance measurement shows roll-off effects in both the inversion and accumulation regions of the C-V curve [4]. These roll- off effects make it impossible for engineers to extract COX directly and use it to monitor thickness variations in production. The roll-off behavior is also dependant on the DC leakage of the gate. Therefore, even for two gate dielectrics with the same physical thickness and area, the lower quality one with higher gate leakage will show the greater roll-off in the C-V curve, which makes it more difficult to monitor thickness variations. Some roll-off effects in the C-V curve are device related [5, 6]. At high frequency the two main factors are channel resistance and contact resistance. These effects could be modeled by a different equivalent circuit model and could be reduced by a new device layout. On the other hand, some of the roll- offs in C-V measurement are related to non-optimized setups, including cabling, connectors, and probe station setup [7]. The fi